SPI Communication Protocol Guide
This note is a record as I learn this communication protocol coming up in work. Serial Peripheral Interface (SPI) is a method/fashion for microcontrollers to send and ask for information from peripherals like sensors, memories/registers, etc. It has shown up frequently for prototyping purposes.
Wiring
SPI uses a four-wire communication system with the following connections:
Controller Out Peripheral In (COPI) - Data line from controller to peripheral device. The microcontroller sends commands and data through this line.
Controller In, Peripheral Out (CIPO) - Data line from peripheral device back to controller. Response data and sensor readings come back through this line.
SCLK (Serial Clock) - Clock signal generated by the controller device. This synchronizes the data transmission between controller and peripheral. Data is typically transferred on the rising or falling edge of this clock.
CS(Chip Select) - Control line that selects which peripheral device is active. Pulled low to activate a device, high to deactivate. Each peripheral needs its own CS line.
Power connections - VCC (3.3V or 5V depending on device) and GND must also be shared between controller and peripheral.
Request and Response
SPI communication is full-duplex, meaning data can be sent and received simultaneously:
Sending Data: The controller sends frames of data on the COPI line and generates clock pulses. Data is sent out in orders and in units of bits. The most common bit ordering in this transmission is the most significant bit (MSB), although some peripherals use the least significant bit too(LSB).
Receiving Data: Simultaneous to receiving requests from the controller, the peripheral responds with data frames on the CIPO line. This means every transmission window is actually an exchange - we send 8 bits and receive 8 bits back. However, note that the response received in this window may or may not (which happens more) be for the request sent out in the same window. Many times, the request sent out in the last window will see its response in the next window. This asynchronous nature often leads to communication errors.
Peripheral Selection
Since SPI uses a shared bus for COPI, CIPO, and SCLK, multiple peripherals can be connected to the same microcontroller:
Individual CS Lines: Each peripheral device gets its own dedicated Chip Select (CS) line connected to a different GPIO pin on the microcontroller. Only one device should have its CS line pulled low at a time.
Device Addressing: Unlike I2C, SPI devices don’t have built-in addresses. The CS line acts as the addressing mechanism - you select which device to talk to by controlling its CS line.
Daisy Chaining: Some SPI devices can be daisy-chained, where the CIPO of one device connects to the COPI of the next, allowing multiple devices to share a single CS line. However, this is less common and device-specific.
SPI Modes
SPI has four modes defined by two parameters - Clock Polarity (CPOL) and Clock Phase (CPHA):
Clock Polarity (CPOL):
- CPOL = 0: Clock is normally low (idle state is low)
- CPOL = 1: Clock is normally high (idle state is high)
Clock Phase (CPHA):
- CPHA = 0: Data is sampled on the first (leading) edge of the clock
- CPHA = 1: Data is sampled on the second (trailing) edge of the clock
The Four Modes:
- Mode 0 (CPOL=0, CPHA=0): Clock idle low, sample on rising edge
- Mode 1 (CPOL=0, CPHA=1): Clock idle low, sample on falling edge
- Mode 2 (CPOL=1, CPHA=0): Clock idle high, sample on falling edge
- Mode 3 (CPOL=1, CPHA=1): Clock idle high, sample on rising edge
The controller and peripheral must use the same SPI mode for proper communication. Check your peripheral’s datasheet to determine which mode it requires - this is usually specified in the electrical characteristics or timing diagram sections.
Timing
From my experience, timing is the most important aspect when working with SPI. Specifically we should pay attention to these aspects:
- Clock Frequency: Has to be equal or less than the unit frequency according to its spec sheet, or make it so such that a clock period is equal to or longer than the specified value.
- Inter-transfer Delays: Many sensors require delays between certain or all transactions. We need to explicitly wait for the specified time.
- Chip Select Timing: Some devices require CS to stay low across multiple transactions, others need it pulsed. This is usually specified in the spec sheet as well.
- SPI Mode: Ensure CPOL/CPHA settings match our peripheral’s requirements.